Data reproduction circuit

ABSTRACT

Provided is a data recovery circuit including an input data phase detection circuit for outputting a gate signal synchronized with a rising phase of input data, a gated multiphase oscillator for instantly generating N-phase clocks based on the gate signal as a trigger, data discriminating and reproducing circuits for outputting sampled data of the input data which are synchronized with the clocks, a continuous clock generation circuit for generating a continuous clock which is a reference clock, continuous clock synchronization circuits for synchronizing the sampled data with the continuous clock and outputting the synchronized sampled data as phase synchronization data, and a phase selector for selecting the phase synchronization data having an optimum discrimination phase with the largest phase margin with respect to the input data and outputting the selected phase synchronization data as recovery data.

TECHNICAL FIELD

The present invention relates to a data recovery circuit for extracting,from input data, a clock synchronized in phase with the input data toreproduce the clock and discriminating and reproducing the input databased on the reproduced clock.

BACKGROUND ART

With the rapid growth of the Internet in recent years, a large scalebroadband connection in a subscriber access network has been required.The mainstream of a system containing the broadband access network is apassive optical networks (PON) system in which a parent station device(optical line terminal (OLT)) is connected to subscriber devices(optical network units (ONUs)) through an optical fiber. The systemstructure is internationally standardized in, for example, Non-PatentDocument 1.

In the PON system, a time division multiplexing (TDM) method ofperforming temporal multiplexing is applied as a method of receivinglight signals from the respective subscriber devices (ONUs). Therefore,a common system capable of containing the plurality of subscriberdevices (ONUs) can be constructed using a single-core optical fibertransmission line, and hence the broadband access network can beeconomically constructed.

The temporally multiplexed signals are burst light signals obtained byintermittently emitting/interrupting the light signals, and hencetechnical problems specific to input burst light signals occur in theparent station device (OLT) which is a receiver device.

A normal optical receiver provided in the parent station device (OLT)includes an optical preamplifier for converting an input burst lightsignal into an electrical signal (input data) having a discriminableamplitude, and a data reproducing (clock and data recovery (CDR))circuit for extracting a clock component from the input data andperforming data recovery based on phase synchronization information. Aphased lock loop (PLL) circuit using a continuous voltage controlledoscillator is normally used as a clock extraction system in the datarecovery circuit. In the PLL system, a control signal substantiallyclose to a DC component is applied as a control signal for frequency andphase control. This is used to suppress fluctuation components (jitters)generated from the oscillator and the PLL. Accordingly, it isessentially difficult for a feedback-controlled clock extraction circuitsuch as the PLL to obtain high-speed response characteristics.

On the other hand, the burst light signals in the PON system describedabove include light signals output from the plurality of subscriberdevices (ONUs) with different transmission distances, and hence therespective burst light signals have various different reception phases.In addition, the frequencies of the burst light signals are synchronizedwith frequencies output from the respective subscriber devices (ONUs),and thus have a relative frequency deviation. Therefore, the datarecovery circuit in the parent station device (OLT) is required to havea function for performing clock extraction and data recovery based onphase synchronization for each of the burst light signals at high speed.However, as described above, in the normal PLL system, it is difficultto realize stable clock extraction from a light signal whose frequencyand phase vary at high speed.

A data recovery circuit for extracting a clock from the burst lightsignal at high speed has been proposed (see, for example, PatentDocument 1). The conventional data recovery circuit generates, fromreceived data, a gating signal synchronized with a rising phase orfalling phase of input data. In an embodiment described in PatentDocument 1, a toggle flip-flop whose output logic is reversed at arising or falling edge of the input data is applied as a gating signalgenerating means. A gated oscillator which performs oscillationoutputting or stopping in instant synchronization with the gating signalis provided, and hence the clock synchronized with the rising phase orfalling phase of the input data is generated. In the embodiment, outputsof two gated oscillators which perform oscillation outputting orstopping based on the positive logic and negative logic of the gatingsignal are combined in an OR gate, and hence clocks instantlysynchronized in phase with the input data can be successively generated.

The conventional data recovery circuit provides a high-speed clockextraction means even when phase information included in data input fromthe respective subscriber devices (ONUs) are uneven and temporallyintermittent burst light signals are input.

Patent Document 1: JP 2005-45525 A

Non-Patent Document 1: IEEE 802.3ah Standard (2004)

DISCLOSURE OF THE INVENTION Problems to be solved by the Invention

However, actual input data has a signal waveform distorted by afluctuation of an optical transmitter provided in the subscriber device(ONU), chromatic dispersion or polarized mode dispersion of an opticalfiber transmission line, or the like. Therefore, there is a problem inthat the distorted waveform has an influence such as deterioration dueto superimposition of a jitter component on the optical receiverprovided in the parent station device (OLT).

FIGS. 8A and 8B illustrate operations of the conventional data recoverycircuit in a case where the jitter component is not included in theinput data and in a case where the jitter component is superimposedthereon. As illustrated in FIGS. 8A and 8B, because a discriminationphase point for an extraction block is normally set based on a fixeddelay time period, when an error of a phase of the extraction clock iscaused by a jitter component, a problem occurs in which discriminationcannot be performed at an optimum phase clock in the conventional datarecovery circuit. In the worst case, discrimination cannot be performed.

The present invention has been made to solve the problems as describedabove. Therefore, an object of the present invention is to obtain a datarecovery circuit capable of reproducing data discriminated from inputdata in an optimum discrimination phase at high speed and outputtingdata synchronized with a reference clock, even when a jitter componentis superimposed on an input temporally intermittent burst light signalfrom a subscriber device (ONU).

Means for Solving the Problems

A data recovery circuit according to the present invention includes: aninput data phase detection circuit for extracting, as a gate signal, asignal synchronized with input data from the input data and outputtingthe gate signal; a gated N-phase oscillator for generating N-phaseclocks obtained by dividing a bit width of the input data into N inphase synchronization with the gate signal output from the input dataphase detection circuit; N data discriminating and reproducing circuitsfor sampling the input data based on the N-phase clocks output from thegated N-phase oscillator and outputting sampled data; a continuous clockgeneration circuit for generating a continuous clock which is areference clock; N continuous clock synchronization circuits forsynchronizing the sampled data output from the N data discriminating andreproducing circuits with the continuous clock output from thecontinuous clock generation circuit and outputting the synchronizedsampled data as phase synchronization data; and a phase selector forselecting, from the phase synchronization data output from the Ncontinuous clock synchronization circuits, phase synchronization datahaving an optimum discrimination phase with a largest phase margin withrespect to the input data and outputting the selected phasesynchronization data as recovery data.

EFFECTS OF THE INVENTION

According to the data recovery circuit in the present invention, aneffect is obtained in which even when the jitter component issuperimposed on the input temporally intermittent burst light signalfrom the subscriber device (ONU), the data discriminated from the inputdata in the optimum discrimination phase at high speed can be reproducedand the data synchronized with the reference clock can be output.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a structure of a data recoverycircuit according to Embodiment 1 of the present invention.

FIG. 2 is a timing chart illustrating operations of an input data phasedetection circuit, a gated multiphase oscillator, and a datadiscriminating and reproducing circuit in the data recovery circuitaccording to Embodiment 1 of the present invention.

FIGS. 3A and 3B illustrate an operation of a continuous clocksynchronization circuit in the data recovery circuit according toEmbodiment 1 of the present invention.

FIG. 4 illustrates a relationship of an allowable jitter amount withrespect to the number of phases N in the data recovery circuit accordingto Embodiment 1 of the present invention and a conventional datarecovery circuit.

FIG. 5 is a block diagram illustrating a structure of a data recoverycircuit according to Embodiment 2 of the present invention.

FIGS. 6A, 6B and 6C illustrate states of stored data of a continuousclock synchronization circuit during an interval including an instant atwhich a burst light signal is input and during an interval for which theburst light signal is stabilized at a constant value in the datarecovery circuit according to Embodiment 2 of the present invention.

FIG. 7 is a block diagram illustrating a structure of a data recoverycircuit according to Embodiment 3 of the present invention.

FIGS. 8A and 8B illustrate operations of the conventional data recoverycircuit in a case where a jitter component is not included in input dataand in a case where the jitter component is superimposed thereon.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention relates to a PON system. In the PON system, aparent station device (OLT) is connected to a subscriber device (ONU)through an optical fiber. An optical receiver is provided in the parentstation device (OLT). The optical receiver includes an opticalpreamplifier and a data recovery circuit.

Embodiments 1 to 3 of the present invention relate to the data recoverycircuit, and more particularly, to a data recovery circuit forextracting a clock at high speed and reproducing and extracting receiveddata at a clock with an optimum phase for a retiming of the receiveddata, even when a jitter component is superimposed on an input signalwaveform of a temporally intermittent burst light signal from asubscriber device (ONU).

Embodiment 1

A data recovery circuit according to Embodiment 1 of the presentinvention is described with reference to FIGS. 1 to 4. FIG. 1 is a blockdiagram illustrating a structure of the data recovery circuit accordingto Embodiment 1 of the present invention. Hereinafter, in each of thedrawings, the same reference symbols indicate the same or correspondingportions.

In FIG. 1, the data recovery circuit according to Embodiment 1 includesan input data phase detection circuit 1, a gated multiphase oscillator(N-phase gated voltage controlled oscillator (GVCO)) 2, N (naturalnumber other than 1) data discriminating and reproducing circuits 3, acontinuous clock generation circuit 4, N continuous clocksynchronization circuits 5, and a phase selector 6.

Next, an operation of the data recovery circuit according to Embodiment1 is described with reference to the attached drawings. FIG. 2 is atiming chart illustrating operations of the input data phase detectioncircuit, the gated multiphase oscillator, and the data discriminatingand reproducing circuit in the data recovery circuit according toEmbodiment 1 of the present invention. In other words, FIG. 2illustrates an operation from data input to data discrimination andrecovery.

In the description of the following circuit operation, circuit logic isdescribed, and hence the influence of a timing deviation such as acircuit delay, which is caused in an actual circuit, is omitted.Specifically, a case where the number of phases N is 4 is described.

The input data phase detection circuit 1 extracts, as a gate signal (b),a signal synchronized with input data (a) from the input data (a), andoutputs the gate signal (b). In other words, when the input data (a) isinput from an optical preamplifier (not shown) provided at the precedingstage, as illustrated in FIG. 2, the input data phase detection circuit1 generates the gate signal (b) selectively synchronized with only arising phase of the input data (a) (Note that the input data phasedetection circuit 1 may generate the gate signal (b) selectivelysynchronized with only a falling phase of the input data (a)). The inputdata phase detection circuit 1 can be constructed using a normal logiccircuit. For simple description, assume that an interval for which thegate signal (b) output here becomes logic L (Low) is shorter than a halfperiod of clocks described later.

Next, the gated multiphase oscillator 2 generates N-phase (N phases)clocks (c) obtained by dividing a bit width BW of the input data (a)into N, in phase synchronization with the gate signal (b) output fromthe input data phase detection circuit 1. In other words, as illustratedin FIG. 2, the gated multiphase oscillator 2 produces oscillation at therising of the gate signal (b) as a trigger during an interval of logic H(High) of the gate signal (b). In this case, an interval of logic L ofthe gate signal (b) is shorter than the half period of the clocksdescribed later, and hence the gated multiphase oscillator 2 does notstop oscillation and thus produces continuous oscillation while phasesynchronization is reproduced again at a trigger point. A specificexample of the gated multiphase oscillator 2 is a four-phase oscillator.Therefore, as illustrated in FIG. 2, the bit width BW of the input data(a) is divided into 4 (=N) and the four-phase (N=0, 1, 2, and 3) clocks(c) are output with delay time periods shifted by BW/4 with respect tothe bit width BW of the input data (a).

Next, the N data discriminating and reproducing circuits 3 sample theinput data (a) based on the N-phase clocks (c) output from the gatedmultiphase oscillator 2 and output sampled data (d). In other words, asillustrated in FIG. 2, upon receiving the clocks (c) from the gatedmultiphase oscillator 2 as sampling clocks, the data discriminating andreproducing circuits 3 output the sampled data (d) which aresynchronized with the respective phase clocks (c) and obtained bysampling the input data (a). The sampling is performed insynchronization with the rising edges of the respective phase clocks(c). Of the sampled data (d), data discriminated based on the clock (c)of N=2 cannot be discriminated because the edge of the input data (a)and the sampling edge are overlapped with each other at substantiallythe same time position, and hence undefined data is output. FIG. 2illustrates the case where the undefined data is logic L. There is astate in which the input data (a) cannot be sampled in addition to theundefined state resulting from the overlap of both the edges. Such astate is also referred to as the undefined state. That is, herein, astate other than the state in which the sampling can be normallyperformed is referred to as the undefined state.

FIGS. 3A and 3B illustrate an operation of a continuous clocksynchronization circuit in the data recovery circuit according toEmbodiment 1 of the present invention. In other words, FIGS. 3A and 3Billustrate an operation during which the sampled data (d) are input tothe continuous clock synchronization circuits 5 and output as phasesynchronization data (e).

The N continuous clock synchronization circuits 5 synchronize thesampled data (d) output from the data discriminating and reproducingcircuits 3 with a continuous clock output from the continuous clockgeneration circuit 4 and output the synchronized sampled data (d) asphase synchronization data (e). In other words, when the sampled data(d) are input, the continuous clock synchronization circuits 5 store thesampled data (d) in order. The continuous clock synchronization circuits5 each includes, for example, a sequential storage device and can beeasily realized using a normal first-in-first-out (FIFO) system.

First, the input of the continuous clock synchronization circuits 5 isdescribed. The sampled data (d) are output as data synchronized with theclocks (c) from the gated multiphase oscillator 2 and stored in thecontinuous clock synchronization circuits 5. The clocks (c) from thegated multiphase oscillator 2 are generated as clocks instantlysynchronized in phase with the input data (a). Therefore, as illustratedin FIG. 3A, the clocks are input as the sampled data (d) on which jittercomponents depending on a fluctuation of the input data (a) aresuperimposed.

Next, the output of the continuous clock synchronization circuits 5 isdescribed. As illustrated in FIG. 3B, the continuous clocksynchronization circuits 5 synchronize the stored sampled data (d) withthe continuous clock output from the continuous clock generation circuit4 and output the synchronized sampled data as the phase synchronizationdata (e). The continuous clock generation circuit 4 is used as areference clock generator of the entire optical receiver. The generatedcontinuous clock includes no jitter component and thus is a clock whosephase is not changed. Therefore, the phase synchronization data (e) areoutput as data from which the jitter components are removed, and whichare synchronized with the continuous clock, that is, the referenceclock.

Next, an operation of the phase selector 6 is described. The phaseselector 6 selects the phase synchronization data (e) having an optimumdiscrimination phase with the largest phase margin with respect to theinput data (a), from the phase synchronization data (e) output from thecontinuous clock synchronization circuits 5, and outputs the selectedphase synchronization data as recovery data (f). As described above, thephase synchronization data (e) from which the jitter components areremoved, and which are synchronized with the continuous clock (referenceclock), are input to the phase selector 6. The phase selector 6includes, for example, a logical table circuit and is set so as toselect the phase synchronization data (e) in the phase having a maximumphase difference, from the phase of the phase synchronization data (e)which is undefined. In the example illustrated in FIGS. 2 and 3, thephase synchronization data (e) in the phase of N=2 is undefined (logicL), and hence the phase synchronization data (e) in the phase of N=0 inwhich the phase difference from the phase of N=2 is maximum is selectedand output as the recovery data (f). The logical table circuit can berealized using a normal gate circuit and easily provided using acomplementary metal oxide semiconductor (CMOS), a filed programable gatearray (FPGA) or the like.

A method of selecting the recovery data (f) with respect to the inputdata (a) can be arbitrarily realized. When the phase selection operationfor selecting the phase in which the phase difference from the undefinedphase is maximum is executed in only one cycle (one time), it is likelyto cause an error. Therefore, the phase selector 6 repeats the phaseselection operation for a plurality of cycles to select the phasesynchronization data (e) in a phase which is selected a largest numberof times as a phase in which the phase difference is maximum, of thephases in which the phase difference is maximum. In other words, thephase selector 6 stores the N-phase phase synchronization data (e)output from the continuous clock synchronization circuits 5 for apredetermined time period (for example, 10 cycles), counts the phase, inwhich the phase difference from the undefined phase is maximum, for apredetermined time period for each phase, and selects the phasesynchronization data (e) in the phase in which the count is largest. Inthe example illustrated in FIG. 2, when the phase of N=2 is in theundefined state for at least 9 cycles (bits) and the phase (N=0) inwhich the phase difference from the undefined phase (N=2) is maximum iscounted for an arbitrary time period (for example, 10 cycles) for eachphase, the phase in which the count is largest is the phase of N=0 inwhich the count is “9”, and hence the phase synchronization data (e) inthe phase of N=0 is selected.

Hereinafter, an effect of Embodiment 1 is described. In a case where thebit width BW of the input data (a) is assumed to be 1 and an apparentbit width becomes 1−dj because of a jitter component dj, when a phasemargin of the data discriminating and reproducing circuit 3 is expressedby dp, it is necessary to satisfy the following Expression (1) to obtainrecovery data with no error.

[Expression 1]

1−dj>dp  (1)

For example, when the phase margin is 270°, dp=270°/360°=0.75, and hencean allowable jitter component dj becomes smaller than 0.25.

Next, the case of the data recovery circuit according to Embodiment 1 isdescribed. The data recovery circuit according to Embodiment 1 samplesthe input data (a) based on the multiphase clocks. Therefore, even whenthe bit width becomes narrower because of the jitter component, it issufficient that a clock edge corresponding to one phase which can besampled during a bit window is input, and hence a condition forobtaining the recovery data (f) with no error can be expressed by thefollowing Expression (2).

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 2} \right\rbrack & \; \\{{1 - {dj}} > \frac{1}{N}} & (2)\end{matrix}$

Note that a minimum value of discrimination sensitivity of the datadiscriminating and reproducing circuit 3 is not taken into accountbecause the value is vary small.

FIG. 4 illustrates a relationship of the allowable jitter amount dj withrespect to the number of phases N using Expressions (1) and (2)described above. As is apparent from FIG. 4, although the allowablejitter amount in the conventional data recovery circuit is 0.25 (UIpp),a jitter amount of up to 0.75 (UIpp) can be allowed in Embodiment 1 inthe case where the number of phases N is 4.

According to Embodiment 1, the data recovery circuit includes the inputdata phase detection circuit 1 for outputting the gate signal (b)synchronized with the rising or falling phase of the input data (a), thegated multiphase oscillator 2 for instantly generating the N-phaseclocks (c) having phase differences in order based on the gate signal(b) as the trigger, the data discriminating and reproducing circuits 3for outputting the sampled data (d) of the input data (a) which aresynchronized with the clocks (c) based on the clocks (c) as the samplingclocks, the continuous clock generation circuit 4 for generating thecontinuous clock which is the reference clock, the continuous clocksynchronization circuits 5 for synchronizing the stored sampled data (d)with the continuous clock and outputting the synchronized sampled dataas the phase synchronization data (e), and the phase selector 6 forselecting the phase synchronization data (e) having the optimumdiscrimination phase with the largest phase margin with respect to theinput data (a) and outputting the selected phase synchronization data asthe recovery data (f). Accordingly, even when the jitter component issuperimposed on the input burst light signal, the data discriminated inthe optimum discrimination phase can be reproduced from the input data(a) at high speed and the data synchronized with the reference clock canbe output.

Embodiment 2

A data recovery circuit according to Embodiment 2 of the presentinvention is described with reference to FIGS. 5 and 6. FIG. 5 is ablock diagram illustrating a structure of the data recovery circuitaccording to Embodiment 2 of the present invention.

In FIG. 5, the data recovery circuit according to Embodiment 2 includesan input data phase detection circuit 1, a gated multiphase oscillator(N-phase GVCO) 2, N data discriminating and reproducing circuits 3, acontinuous clock generation circuit 4, N continuous clocksynchronization circuits 5, a phase selector 6, and an input patterndetection circuit 7.

Next, an operation of the data recovery circuit according to Embodiment2 is described with reference to the attached drawings.

Embodiment 2 is a modified example of Embodiment 1 described above. Thesampling operation of the input data, the continuous clocksynchronization operation, and the phase selection operation are similarto the operations of Embodiment 1, and thus the descriptions thereof areomitted. Hereinafter, an input pattern detection operation of the inputpattern detection circuit 7 is described.

When the input data (a) is input, the input pattern detection circuit 7generates a logic H signal only when an input data pattern during anarbitrary time width (bit interval) is matched with a reference patternheld in advance in the input pattern detection circuit 7. The inputpattern detection circuit 7 supplies the logic H signal as a resetsignal to each of the N continuous clock synchronization circuits 5. Thereference pattern is equal to a fixed bit pattern included in advance inthe input data (a), that is, the input burst light signal.

The storage operation of each of the N continuous clock synchronizationcircuits 5 is controlled in response to the reset signal. Stored dataare discarded and erased at the instant at which the reset signal isinput, and the storage of the sampled data (d) is started again. Thecontinuous clock synchronization circuits 5 each include, for example, asequential storage device with reset signal. When the reset signal isinput, the storage of the sampled data (d) is started by afirst-in-first-out (FIFO) system.

Hereinafter, an effect of Embodiment 2 is described. FIGS. 6A, 6B and 6Cillustrate states of stored data of the continuous clock synchronizationcircuit 5 during an interval (α) including an instant at which the burstlight signal is input and during an interval (β) for which the burstlight signal is stabilized at a constant value. In general, asillustrated in FIG. 6A, immediately after the burst light signal isinput, distorted data are normally reproduced because of responsecharacteristics of an optical preamplifier (not shown) or the like whichis used at the preceding stage. In Embodiment 2, clocks depending on theinput data are generated, and hence data synchronized with distortedclocks are input. Therefore, as illustrated in FIGS. 6B and 6C, unlikethe stored data during the interval (β) for which the burst light signalis stabilized at the constant value, the stored data during the interval(α) immediately after the burst light signal is input includes an error,and thus stores erroneous operation signals. In order to disable theerroneous operation signals and to store only effective normal data, thefixed bit pattern set in advance is inserted to an arbitrary intervalbetween the input data (a). When the fixed bit pattern is matched withthe reference pattern held in advance in the input pattern detectioncircuit 7, the continuous clock synchronization circuits 5 desirablystart the sequential storage operation.

According to Embodiment 2, the data recovery circuit includes the inputdata phase detection circuit 1, the gated multiphase oscillator 2, thedata discriminating and reproducing circuits 3, the continuous clockgeneration circuit 4, the continuous clock synchronization circuits 5which start the sequential storage operation of the sampled data whenthe reset signal is input, the phase selector 6, and the input patterndetection circuit 7 for outputting the reset signal only when the fixedbit pattern of the input data is matched with the reference pattern.Accordingly, even when the burst light signal is input and erroneousdata is included during the interval (α) immediately after the inputthereof, the data discriminated in the optimum discrimination phase canbe reproduced from the input data at high speed and the datasynchronized with the reference clock can be output.

Embodiment 3

A data recovery circuit according to Embodiment 3 of the presentinvention is described with reference to FIG. 7. FIG. 7 is a blockdiagram illustrating a structure of the data recovery circuit accordingto Embodiment 3 of the present invention.

In FIG. 7, the data recovery circuit according to Embodiment 3 includesan input data phase detection circuit 1, a gated multiphase oscillator(N-phase GVCO) 2, N data discriminating and reproducing circuits 3, acontinuous clock generation circuit 4, N continuous clocksynchronization circuits 5, a phase selector 6, and a frequency/phasesynchronization circuit 8.

The frequency/phase synchronization circuit 8 includes a gatedoscillator 81 and a frequency/phase comparator 82.

Next, an operation of the data recovery circuit according to Embodiment3 is described with reference to the attached drawings.

Embodiment 3 is a modified example of Embodiment 1 described above. Thesampling operation of the input data, the continuous clocksynchronization operation, and the phase selection operation are similarto the operations of Embodiment 1, and thus the descriptions thereof areomitted. Hereinafter, an operation of the frequency/phasesynchronization circuit 8 is described.

The gated oscillator 81 included in the frequency/phase synchronizationcircuit 8 has the same circuit structure as the gated multiphaseoscillator 2 and is substantially equal in oscillation frequency to thegated multiphase oscillator 2. The frequency/phase comparator 82included in the frequency/phase synchronization circuit 8 detects anerror between a frequency/phase of a clock output from the gatedoscillator 9 and a frequency/phase of the continuous clock generated bythe continuous clock generation circuit 4 and outputs an error signal asa frequency control signal.

The gated multiphase oscillator 2 includes, for example, a ringoscillation circuit. The ring oscillation circuit includes: a pluralityof (N) delay elements whose delay amounts are arbitrarily controlledbased on the frequency control signal; and a gating circuit foroutputting AND results between outputs of the N delay elements and thegate signal (b). N outputs of the gating circuit correspond to N-phaseclocks (c) with relative phase differences (delay differences). A gatesignal of the gated oscillator 81 is logically fixed, thereby performingcontinuous oscillation.

The gated oscillator 81 changes the oscillation frequency based on thefrequency control signal to minimize the error signal from thefrequency/phase comparator 82. Therefore, in a steady state, the outputclock of the continuous clock generation circuit 4 which is thereference clock of the optical receiver is synchronized infrequency/phase with the output clock of the gated oscillator 81. Thesynchronization information is transferred as the frequency controlsignal to the gated multiphase oscillator 2. As a result, theoscillation frequency of the gated multiphase oscillator 2 is alsocontrolled so as to be synchronized with the continuous clock.

Hereinafter, an effect of Embodiment 3 is described. When thefrequency/phase synchronization circuit 8 is not provided, theoscillation frequency of the gated multiphase oscillator 2 isindependently determined based on constants resulting from aself-circuit structure, and therefore includes a frequency deviationfrom the output clock of the continuous clock generation circuit 4 whichis the reference clock of the optical receiver. When the frequencydeviation is large, an input data speed is not matched with an outputdata speed in the continuous clock synchronization circuits 5 serving asthe sequential storage device, and hence a problem such as a storageoverflow occurs. Even when the frequency deviation is suppressed bycontriving circuit constants, it is difficult to performself-oscillation at a stable frequency for a change in ambienttemperature or the like. When the frequency/phase synchronizationcircuit 8 provided in Embodiment 3 is applied, it is possible to providethe stable gated multiphase oscillator 2 which is synchronized in phasewith the input data at high speed and synchronized in frequency with thecontinuous clock generation circuit 4.

According to Embodiment 3, the data recovery circuit includes the inputdata phase detection circuit 1, the gated multiphase oscillator 2 forgenerating the clocks synchronized with the continuous clock based onthe frequency control signal, the N-phase data discriminating andreproducing circuits 3, the continuous clock generation circuit 4, thecontinuous clock synchronization circuits 5, the phase selector 6, andthe frequency/phase synchronization circuit 8 for outputting, as thefrequency control signal, the synchronization information of thecontinuous clock generated by the continuous clock generation circuit 4.Accordingly, even when the gated multiphase oscillator 2 includes thefrequency deviation from the continuous clock of the continuous clockgeneration circuit 4, the data discriminated in the optimumdiscrimination phase can be reproduced from the input data with thestable frequency oscillation clock at high speed and the datasynchronized with the reference clock can be output.

1. A data recovery circuit, comprising: an input data phase detectioncircuit for extracting, as a gate signal, a signal synchronized withinput data from the input data and outputting the gate signal; a gatedN-phase oscillator for generating N-phase clocks obtained by dividing abit width of the input data into N in phase synchronization with thegate signal output from the input data phase detection circuit; N datadiscriminating and reproducing circuits for sampling the input databased on the N-phase clocks output from the gated N-phase oscillator andoutputting sampled data; a continuous clock generation circuit forgenerating a continuous clock which is a reference clock; N continuousclock synchronization circuits for synchronizing the sampled data outputfrom the N data discriminating and reproducing circuits with thecontinuous clock output from the continuous clock generation circuit andoutputting the synchronized sampled data as phase synchronization data;and a phase selector for selecting, from the phase synchronization dataoutput from the N continuous clock synchronization circuits, phasesynchronization data having an optimum discrimination phase with alargest phase margin with respect to the input data and outputting theselected phase synchronization data as recovery data.
 2. A data recoverycircuit according to claim 1, further comprising an input patterndetection circuit for outputting a reset signal when a fixed bit patternincluded in the input data matches with a reference pattern held inadvance, wherein the N continuous clock synchronization circuits start asequential storage operation of the sampled data when the reset signalis input.
 3. A data recovery circuit according to claim 1, furthercomprising a frequency/phase synchronization circuit for outputting, asa frequency control signal, synchronization information of thecontinuous clock generated by the continuous clock generation circuit,wherein the gated N-phase oscillator generates clocks synchronized withthe continuous clock based on the frequency control signal.
 4. A datarecovery circuit according to claim 1, wherein: the input data phasedetection circuit generates the gate signal synchronized with a risingphase or falling phase of the input data; and an interval in which thegate signal is logic L is shorter than a half period of the clocksgenerated from the gated N-phase oscillator.
 5. A data recovery circuitaccording to claim 1, wherein the gated N-phase oscillator generates theN-phase clocks with delay time periods relatively shifted by 1/N of thebit width of the input data during an interval in which the gate signalis logic H, at a rising of the gate signal as a trigger.
 6. A datarecovery circuit according to claim 1, wherein the N data discriminatingand reproducing circuits receive the clocks as sampling clocks andoutput sampled data which are results obtained by sampling the inputdata synchronized with rising edges of the clocks.
 7. A data recoverycircuit according to claim 1, wherein each of the N continuous clocksynchronization circuits includes a sequential storage device, storesthe sampled data by a first-in-first-out system, and outputs the storedsampled data as the phase synchronization data in synchronization withthe continuous clock.
 8. A data recovery circuit according to claim 1,wherein the phase selector repeats, for a plurality of cycles, an phaseselection operation for selecting a phase in which a phase differencefrom an undefined phase is maximum in the phase synchronization data, toselect phase synchronization data corresponding to a phase which isselected a largest number of times as the phase in which the phasedifference is maximum, of phases in which the phase difference ismaximum, and to output the selected phase synchronization data as therecovery data.
 9. A data recovery circuit according to claim 2, whereineach of the N continuous clock synchronization circuits comprises asequential storage device with the reset signal, starts, when the resetsignal is input, storing the sampled data by a first-in-first-outsystem, and outputs the stored sampled data as the phase synchronizationdata in synchronization with the continuous clock.
 10. A data recoverycircuit according to claim 3, wherein the frequency/phasesynchronization circuit includes: a gated oscillator which has the samecircuit structure as the gated N-phase oscillator and is substantiallyequal in oscillation frequency to the gated N-phase oscillator; and afrequency/phase comparator for detecting an error between afrequency/phase of a clock output from the gated oscillator and afrequency/phase of the continuous clock output from the continuous clockgeneration circuit and outputting an error signal as the frequencycontrol signal.
 11. A data recovery circuit according to claim 10,wherein: the gated N-phase oscillator comprises a ring oscillationcircuit comprising: N delay elements whose delay amounts are arbitrarilycontrolled based on the frequency control signal; and a gating circuitfor outputting AND results between outputs of the N delay elements andthe gate signal; and N outputs of the gating circuit correspond to theN-phase clocks having relative phase differences.